WM8771
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DAC OUTPUT PHASE
The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted
REGISTER ADDRESS
BIT
7:0
LABEL
PH[7:0]
DEFAULT
00000000
DESCRIPTION
10010
Bit
0
DAC
Phase
DAC Phase
DAC1L
DAC1R
1 = invert
1 = invert
1 = invert
1 = invert
1 = invert
1 = invert
1 = invert
1 = invert
1
2
3
4
5
6
7
DAC2L
DAC2R
DAC3L
DAC3R
DAC4L
DAC4R
ADC GAIN CONTROL
Control bits LAG[4:0] and RAG[4:0] control the ADC input gain, allowing the user to attenuate the
ADC input signal to match the full-scale range of the ADC. The gain is independently adjustable on
left and right inputs. Left and right inputs may also be independently muted. The LRBOTH control bit
allows the user to write the same attenuation value to both left and right volume control registers. The
ADC volume and mute also applies to the bypass signal path
REGISTER
ADDRESS
BIT
4:0
LABEL
LAG[4:0]
MUTE
DEFAULT
DESCRIPTION
11001
Attenuation
ADCL
01100
(0dB)
0
Attenuation data for Left channel ADC gain in 1dB steps. See Table
11
5
Mute for Left channel ADC:
0: Mute off
1: Mute on
6
LRBOTH
RAG[4:0]
0
Setting LRBOTH will write the same gain value to LAG[4:0] and
RAG[4:0]
11010
4:0
01100
(0dB)
0
Attenuation data for right channel ADC gain in 1dB steps. See Table
11
Attenuation
ADCR
5
6
MUTE
Mute for Right channel ADC:
0: Mute off
]1: Mute on
LRBOTH
0
Setting LRBOTH will write the same gain value to RAG[4:0] and
LAG[4:0]
PP Rev 2.0 December 2001
30
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
