Product Preview
WM8771
10010
7:0
0
PHASE
DZCEN
ATC
00000000
Controls phase of DAC outputs
0: Sets non inverted output phase
1: inverts phase of DAC output
DAC Digital Volume Zero Cross Enable:
0: Zero Cross detect disabled
1: Zero Cross detect enabled
Phase swaps
10011
0
0
DAC Control
Attenuator Control
1
0: All DACs use attenuations as programmed.
1: Right channel DACs use corresponding left DAC
attenuations
2
IZD
0
Infinite zero detection circuit control and automute control
0: Infinite zero detect disabled
1: Infinite zero detect enabled
7:4
PL[3:0]
1001
DAC Output Control
PL[3:0]
Left
Right
PL[3:0]
Left
Right
Output
Output
Output
Output
0000
0001
0010
0011
0100
0101
0110
0111
Mute
Left
Mute
Mute
Mute
Mute
Left
1000
1001
1010
1011
1100
1101
1110
1111
Mute
Left
Right
Right
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
Mute
Left
Right
Right
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
Left
Right
(L+R)/2
Left
Right
(L+R)/2
Left
10100
3:0
4
DMUTE[3:0]
MUTEALL
RECEN[2:0]
DZFM
0000
0
DAC channel soft mute enables:
0: mute disabled
DAC and
REC Mute
1: mute enabled
DAC channel master soft mute. Mutes all DAC channels:
0: mute disabled
1: mute enabled
7:5
7:4
000
0000
REC output enable
0 : REC outputs muted
1: REC outputs enabled
10101
Selects the ouput for ZFLG1 and ZFLG2 pins (see Table 9).
DAC Control
1: indicates 1024 consecutive zero input samples on the
channels selected
0: indicates at least one of selected channels has non
zero sample in last 1024 inputs
3:0
1:0
DEEMP
0000
00
De-emphasis mode select:
0 : Normal Mode
1: De-emphasis Mode
Interface format select
FMT[1:0]
PP Rev 2.0 December 2001
35
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
