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WM8771
11000
0
PDWN
0
Power Down Mode Select:
Powerdown Control
0 : Normal Mode
1: Power Down Mode
The ADC and DACs may also be powered down by setting the ADCD and DACD disable bits. Setting
ADCD will disable the ADC and select a low power mode. The ADC digital filters will be reset and will
reinitialise when ADCD is reset. Each Stereo DAC channel has a separate disable DACD[3:0].
Setting DACD for a channel will disable the DACs and select a low power mode, also connecting the
DAC outputs to VMID. Resetting DACD will reinitialise the digital filters.
REGISTER ADDRESS
BIT
1
LABEL
ADCD
DEFAULT
1
DESCRIPTION
ADC Disable:
0 : Normal Mode
1: Power Down Mode
DAC Disable:
11000
Powerdown Control
5:2
DACD[3:0]
1
0 : Normal Mode
1: Power Down Mode
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and
right channel DACs from the next audio input sample. No update to the attenuation registers is
required for ATC to take effect.
REGISTER ADDRESS
BIT
1
LABEL
ATC
DEFAULT
0
DESCRIPTION
10011
Attenuator Control Mode:
DAC Channel Control
0 : Right channels use Right
attenuations
1: Right Channels use Left
attenuations
INFINITE ZERO DETECT
Setting the IZD register bit will enable the internal infinite zero detect function:
REGISTER ADDRESS
BIT
2
LABEL
IZD
DEFAULT
0
DESCRIPTION
10011
Infinite zero Mute Enable
0 : disable infinite zero mute
1: enable infinite zero Mute
DAC Channel Control
With IZD enabled, applying 1024 consecutive input samples to all 8 DAC channels will cause all
outputs to be muted to VMID. Mute will be removed as soon as any channel receives a non-zero input.
ZERO FLAG OUTPUT
The DZFM control bits allow the selection of the eight DAC channel zero flag bits for output on the
ZFLAG1 and ZFLAG2 pins. A ‘1’ on ZFLAG1 or ZFLAG2 indicates 1024 consecutive zero input
samples to the channels selected.
REGISTER ADDRESS
BIT
7:4
LABEL
DEFAULT
0000
DESCRIPTION
10101
DZFM[3:0]
Selects the output for ZFLG1 and
ZFLG2 pins (see Table 9). A ‘1’
indicates 1024 consecutive zero
input samples on the channels
selected.
Zero Flag Select
PP Rev 2.0 December 2001
27
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
