WM8771
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DSP EARLY MODE
In DSP early mode, the MSB of DAC channel 1 left data is sampled by the WM8771 on the second
rising edge on BCLK following a DACLRC rising edge. DAC channel 1 right and DAC channels 2, 3
and 4 data follow DAC channel 1 left data (Figure 14).
1 BCLK
1 BCLK
1/fs
DACLRC
BCK
CHANNEL 1
LEFT
CHANNEL 1
RIGHT
CHANNEL 2
LEFT
CHANNEL 4
RIGHT
NO VALID DATA
DIN1
1
2
n
1
2
n
1
2
n
n-1
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 14 DSP Early Mode Timing Diagram – DAC data input
The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of
BCLK following a low to high ADCLRC transition and may be sampled on the rising edge of BCLK.
The right channel ADC data is contiguous with the left channel data (Figure 15)
1 BCLK
1 BCLK
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n
1
2
n
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 15 DSP Early Mode Timing Diagram – ADC data output
PP Rev 2.0 December 2001
20
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
