WM8771
Product Preview
CONTROL INTERFACE OPERATION
The WM8771 is controlled using a 3-wire serial interface in either an SPI compatible configuration or
a CCB (Computer Control Bus) configuration.
The interface configuration is determined by the state of the CE pin on the rising edge of the
RESETB pin. If the CE pin is low on the rising edge of RESETB, CCB configuration is selected. If CE
is high on the rising edge of RESETB, SPI compatible configuration is selected.
The control interface is 5V tolerant, meaning that the control interface input signals CE, CL and DI
may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by DVDD.
RESETB and DACMUTE are also 5V tolerant.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
DI is used for the program data, CL is used to clock in the program data and CE is used to latch the
program data. DI is sampled on the rising edge of CL. The 3-wire interface protocol is shown in
Figure 18.
CE
CL
DI
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 18 3-wire SPI compatible Interface
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
3. CE is edge sensitive – the data is latched on the rising edge of CE.
CCB INTERFACE MODE
CCB Interface mode allows multiple devices to be controlled off a common 3-wire bus. Each device
on the 3-wire bus has its own identifying address. The WM8771 supports write only CCB interface
mode.
DI is used for the device address and program data and CL is used to clock in the address and data
on DI. DI is sampled on the rising edge of CL. CE indicates whether the data on DI is the device
address or program data. The eight clocks before a rising edge on CE will clock in the device
address. The device address is latched on the rising edge of CE. The sixteen clocks before a falling
edge on CE will clock in the program data. The program data is latched on the falling edge of CE.
CE
CL
DI
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D14 D15
Figure 19 CCB Interface – CL stopped low
PP Rev 2.0 December 2001
22
w