WM8771
Product Preview
POWERDOWN MODES
The WM8771 has powerdown control bits allowing specific parts of the WM8771 to be powered off
when not being used. The 8-channel input source selector and input buffer may be powered down
using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1l/R to AIN8L/R)
are switched to a buffered VMIDADC. Control bit ADCPD powers off the ADC and also the ADC input
PGAs. The four stereo DACs each have a separate powerdown control bit, DACPD[3:0] allowing
individual stereo DACs to be powered off when not in use. The analogue output buffer may also be
powered down by setting OUTPD[3:0]. OUTPD[3:0] also switches the analogue outputs VOUTL/R to
VMIDDAC to maintain a dc level on the output. Setting AINPD, ADCPD, DACPD[3:0] and
OUTPD[3:0] will powerdown everything except the references VMIDADC, ADCREF and VMIDDAC.
These may be powered down by setting PDWN. Setting PDWN will override all other powerdown
control bits. It is recommended that the 8-channel input mux and buffer, ADC, DAC and output
buffers are powered down before setting PDWN. The default is for all powerdown bits to be set
except PDWN.
PP Rev 2.0 December 2001
16
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
