WM8771
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AUDIO INTERFACE FORMATS
Audio data is applied to the internal DAC filters, or output from the ADC filters, via the Digital Audio
Interface. 5 popular interface formats are supported:
•
•
•
•
•
Left Justified mode
Right Justified mode
I2S mode
DSP Early mode
DSP Late mode
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the
exception of 32 bit right justified mode, which is not supported.
In left justified, right justified and I2S modes, the digital audio interface receives DAC data on the
DIN1/2/3/4 inputs and outputs ADC data on DOUT. Audio Data for each stereo channel is time
multiplexed with ADCLRC/DACLRC indicating whether the left or right channel is present.
ADCLRC/DACLRC is also used as a timing reference to indicate the beginning or end of the data
words.
In left justified, right justified and I2S modes, the minimum number of BCLKs per DACLRC/ADCLRC
period is 2 times the selected word length. ADCLRC/DACLRC must be high for a minimum of word
length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on
ADCLRC/DACLRC is acceptable provided the above requirements are met.
In DSP early or DSP late mode, all 8 DAC channels are time multiplexed onto DIN1. DACLRC is
used as a frame sync signal to identify the MSB of the first word. The minimum number of BCLKs
per DACLRC period is 8 times the selected word length. Any mark to space ratio is acceptable on
DACLRC provided the rising edge is correctly positioned. The ADC data may also be output in DSP
early or late modes, with ADCLRC used as a frame sync to identify the MSB of the first word. The
minimum number of BCLKs per ADCLRC period is 2 times the selected word length
LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN1/2/3/4 is sampled by the WM8771 on the first rising edge of
BCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on
the same falling edge of BCLK as ADCLRC and may be sampled on the rising edge of BCLK.
ADCLRC and DACLRC are high during the left samples and low during the right samples (Figure 11).
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
DIN1/2/3/4/
DOUT
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Figure 11 Left Justified Mode TIming Diagram
PP Rev 2.0 December 2001
18
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
