WM8771
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tRCES tRCLH
RESETB
CE
tCP tCS
tCH
tSCY
tSCL
tSCH
CL
DI
A7
D15
tDSU
tDHO
Figure 7 3 wire CCB compatible Interface Input Timing Information – CL stopped low
tRCES tRCLH
RESETB
tCH
tCP tCS
CE
tSCY
tSCL
tSCH
CL
DI
A7
D15
tDSU
tDHO
Figure 8 3 wire CCB compatible Interface Input Timing Information – CL stopped high
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
CE to RESETB setup time
tRCES
20
ns
RESETB to CL hold time
DI to CL setup time
CL to DI hold time
CL to CE setup time
CE to CL wait time
CL to CE hold time
CL pulse width high
CL pulse width low
CL pulse cycle time
tRCLH
tDSU
tDHO
tCS
20
20
20
20
20
20
30
30
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCP
t
CH
tSCH
tSCL
tSCY
Table 5 3 wire CCB compatible Interface Input Timing Information
PP Rev 2.0 December 2001
12
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
