WM8766
Preliminary Technical Data
REGISTER ADDRESS
0000011
BIT
LABEL
DEFAULT
DESCRIPTION
In left/right/I2S Modes:
2
LRP
0
Interface Control
LRCLK Polarity (normal)
0 : Normal LRCLK polarity
1: Inverted LRCLK polarity
In DSP Mode:
0 : Early DSP mode
1: Late DSP mode
By default, LRCLK and DIN1/2/3 are sampled on the rising edge of BCLK and should ideally change
on the falling edge. Data sources that change LRCLK and DIN1/2/3 on the rising edge of BCLK can
be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the
inverse of that shown in Figure 11, Figure 12, Figure 13, Figure 14, and Figure 15.
REGISTER ADDRESS
0000011
BIT
LABEL
DEFAULT
DESCRIPTION
BCLK Polarity (DSP Modes):
0: Normal BCLK polarity
1: Inverted BCLK polarity
3
BCP
0
Interface Control
The IWL[1:0] bits are used to control the input word length.
REGISTER ADDRESS
0000011
BIT
LABEL
IWL
DEFAULT
DESCRIPTION
Input Word Length:
00 : 16 bit data
5:4
00
Interface Control
[1:0]
01: 20 bit data
10: 24 bit data
11: 32 bit data
Note: 32-bit right justified mode is not supported.
In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the
DAC is programmed to receive 16 or 20 bit data, the WM8766 pads the unused LSBs with zeros. If
the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.
Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that LRCLK is high for a
minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
A number of options are available to control how data from the Digital Audio Interface is applied to
the DAC channels.
PTD Rev 2.3 February 2004
20
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
