Preliminary Technical Data
WM8766
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function:
REGISTER ADDRESS
0000010
BIT
LABEL
DEFAULT
DESCRIPTION
4
IZD
0
Infinite Zero Mute Enable
DAC Channel Control
0 : Disable inifinite zero mute
1: Enable infinite zero mute
With IZD enabled, applying 1024 consecutive zero input samples to each stereo channel will cause
that stereo channel outputs to be muted to VMID. Mute will be removed as soon as that stereo
channel receives a non-zero input.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are
applied to the left and right DACs:
REGISTER ADDRESS
0000010
BIT
LABEL
DEFAULT
DESCRIPTION
8:5
PL[3:0]
1001
PL[3:0]
Left
Right
Output
Output
DAC Control
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Mute
Left
Mute
Mute
Mute
Mute
Left
Right
(L+R)/2
Mute
Left
Left
Right
(L+R)/2
Mute
Left
Left
Left
Right
Right
Right
Right
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits:
REGISTER ADDRESS
0000011
BIT
LABEL
FMT
DEFAULT
DESCRIPTION
Interface Format Select:
00 : Right justified mode
01: Left justified mode
10: I2S mode
1:0
00
Interface Control
[1:0]
11: DSP (early or late) mode
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCLK. If this
bit is set high, the expected polarity of LRCLK will be the opposite of that shown in Figure 11, Figure
12 and Figure 13. Note that if this feature is used as a means of swapping the left and right
channels, a 1 sample phase difference will be introduced. In DSP modes, the LRP register bit is
used to select between early and late modes.
PTD Rev 2.3 February 2004
19
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
