Preliminary Technical Data
WM8766
DSP EARLY MODE
In DSP early mode, the MSB of DAC channel 1 left data is sampled by the WM8766 on the second
rising edge on BCLK following a LRCLK rising edge. DAC channel 1 right and DAC channels 2 and 3
data follow DAC channel 1 left data (Figure 14).
Figure 14 DSP Early Mode Timing Diagram – DAC Data Input
DSP LATE MODE
In DSP late mode, the MSB of DAC channel 1 left data is sampled by the WM8766 on the first BCLK
rising edge following a LRCLK rising edge. DAC channel 1 right and DAC channels 2 and 3 data
follow DAC channel 1 left data (Figure 15).
Figure 15 DSP Late Mode Timing Diagram – DAC Data Input
In both early and late DSP modes, DACL1 is always sent first, followed immediately by DACR1 and
the data words for the other 6 channels. No BCLK edges are allowed between the data words. The
word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right.
POWERDOWN MODES
The WM8766 has powerdown control bits allowing specific parts of the WM8766 to be powered off
when not being used. The three stereo DACs each have a separate powerdown control bit,
DACPD[2:0] allowing individual stereo DACs to be powered off when not in use. Setting DACPD[2:0]
will powerdown everything except the reference VMID may be powered down by setting PDWN.
Setting PDWN will override all other powerdown control bits. It is recommended that the DACs are
powered down before setting PDWN.
PTD Rev 2.3 February 2004
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