WM8766
Preliminary Technical Data
MASTER POWERDOWN
This control bit powers down the references for the whole chip. Therefore for complete powerdown,
all DACs should be powered down first before setting this bit.
REGISTER ADDRESS
0001010
BIT
LABEL
DEFAULT
DESCRIPTION
Master Power Down Bit:
0: Not powered down
1: Powered down
4
PWRDNALL
0
Interface Control
MASTER MODE SELECT
Control bit MS selects between audio interface Master and Slave Modes. In Master mode LRCLK
and BCLK are outputs and are generated by the WM8766. In Slave mode LRCLK and BCLK are
inputs to WM8766.
REGISTER ADDRESS
0001010
BIT
LABEL
DEFAULT
DESCRIPTION
5
MS
0
DAC Audio Interface Master/Slave
Mode Select:
Interface Control
0: Slave mode
1: Master mode
MASTER MODE LRCLK FREQUENCY SELECT
In Master mode the WM8766 generates LRCLK and BCLK. These clocks are derived from the
master clock and the ratio of MCLK to LRCLK is set by RATE.
REGISTER ADDRESS
0001010
BIT
LABEL
DEFAULT
DESCRIPTION
Master Mode
8:6 RATE [2:0]
010
Interface Control
MCLK:LRCLK Ratio Select:
000: 128fs
001: 192fs
010: 256fs
011: 384fs
100: 512fs
101: 768fs
MUTE PIN DECODE
The MUTE pin can either be used as an output or an input. When used as an input the MUTE pins
action can be controlled by setting the DZFM bit to select the corresponding DAC for applying the
MUTE to. As an output its meaning is selected by the DZFM control bits. By default selecting the
MUTE pin to represent if DAC1 has received more than 1024 midrail samples will cause the MUTE
pin to assert a softmute on DAC1. Disabling the decode block will cause any logical high on the
MUTE pin to apply a softmute to all DAC’s.
REGISTER ADDRESS
0001100
BIT
LABEL
DEFAULT
DESCRIPTION
MUTE Pin Decode Disable:
0: MUTE pin decode enable
1: MUTE pin decode disable
6
MPD
0
MUTE Control
PTD Rev 2.3 February 2004
24
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
