Advanced Information
WM8753L
AUDIO SAMPLE RATES
The WM8753L has two modes of operation for the HiFi DAC, ADC and voice DAC sample rates,
selectable using control bit SRMODE:
HiFi Codec Mode: SRMODE=0. HiFi DAC and stereo ADC used for high quality playback and record.
The Voice DAC is unused. Sample rate control is via control bits SR[4:0] and USB.
HiFi DAC + Voice Codec Mode: SRMODE=1. HiFi DAC is used for high quality playback; Stereo (or
mono) ADC and voice DAC are used for voice record and playback. HiFi DAC Sample rate is
controlled by SR[4:0] and USB. Voice Codec sample rate is controlled by PSR.
In either mode of operation the ADCs and DACs may be powered off if not required to allow e.g. HiFi
DAC playback only, with ADCs disabled. The HiFi DAC sample rate is always controlled by SR[4:0]
and USB.
HIFI CODEC MODE
In this mode the Voice DAC is unused and the stereo ADC is used for HiFi record.The WM8753L may
be configured to run from a clock generated by the on-chip PLL or may be driven from an external
clock connected to the MCLK pin. The WM8753L supports a wide range of master clock frequencies
on the MCLK pin, and can generate many commonly used audio sample rates directly from the
master clock. In HiFi Codec Mode the ADC and DAC do not need to run at the same sample rate;
several different combinations are possible.
There are two clocking modes:
•
•
‘Normal’ mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their
multiples (Note: fs refers to the ADC or DAC sample rate, whichever is faster)
USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use
in systems with a USB interface, and eliminates the need for the internal PLL to
generate the clock frequency for the audio codec.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R6 (06h)
Sample Rate
Control (1)
8
SRMODE
0
ADC Sample rate mode
0 – ADC sample rate selected
by SR[4:0] and USB
1 – ADC sample rate selected
by PSR
[5:1]
0
SR [4:0]
USB
00000
0
Sample Rate Control
Clocking Mode Select
1 = USB Mode
0 = ‘Normal’ Mode
Table 66 Clocking and Sample Rate Control
The clocking of the WM8753L Hi-Fi Codec is controlled using the MCLK1DIV2, USB, and SR control
bits. SR allows the user to change the ADC and DAC sample rates without changing the master clock
frequency. Setting the MCLK1DIV2 bit divides MCLK by two internally. The USB bit selects between
‘Normal’ and USB mode. Each value of SR[4:0] selects one combination of MCLK division ratios and
hence one combination of sample rates (see next page). Since all sample rates are generated by
dividing MCLK, their accuracy depends on the accuracy of MCLK. If MCLK changes, the sample
rates change proportionately.
Note that some sample rates (e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their
target value by a very small amount. This is not audible, as the maximum deviation is only 0.27%
(8.0214kHz instead of 8kHz in USB mode). By comparison, a half-tone step corresponds to a 5.9%
change in pitch.
AI Rev 3.1 June 2004
68
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
