WM8753L
Advanced Information
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R54 (36h)
PLL1 Control (2)
Integer (N) part of PLL1 input/output
frequency ratio. Use values greater
than 5 and less than 13.
8:5
PLL1N
1000
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 22-digit binary number).
3:0
8:0
PLL1K [21:18]
PLL1K [17:9]
0011
024h
R55 (37h)
PLL1 Control (3)
R56 (38h)
8:0
PLL1K [8:0]
1Bah
PLL1 Control (4)
Table 63 PLL1 Frequency Ratio Control
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R58 (3Ah)
PLL2 Control (2)
Integer (N) part of PLL2 input/output
frequency ratio. Use values greater
than 5 and less than 13.
8:5
PLL2N
1000
Fractional (K) part of PLL2
input/output frequency ratio (treat as
one 22-digit binary number)
3:0
8:0
PLL2K [21:18]
PLL2K [17:9]
0011
024h
R59 (3Bh)
PLL2 Control (2)
R60 (3Ch)
8:0
PLL2K [8:0]
1Bah
PLL2 Control (3)
Table 64 PLL2 Frequency Ratio Control
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings
are shown below.
MCLK
(MHz)
(F1)
DESIRED
OUTPUT
(MHz)
F2
(MHz)
MCLK
DIV2
PLL
OUT
DIV2
CLK
OUT
DIV2
R
N
(Hex)
K
(Hex)
11.91
11.91
12
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7.5833
8.2539
7.5264
8.192
7
8
7
8
6
7
6
6
9
A
9
9
9
9
7
8
6
7
6
7
25545F
103FF8
21B08A
C49BA
3CA2F5
23F54A
116873
34E81B
1A1CAC
F5C29
12
13
6.9474
7.5618
6.272
13
14.4
14.4
19.2
19.2
19.68
19.68
19.8
19.8
24
6.8267
9.408
10.24
9.1785
9.9902
9.1229
9.9297
7.5264
8.192
B6D25
3F6028
7DDBE
3B8028
21B08A
C49BA
3CA2F5
23F54A
2C2B25
1208A6
24
26
6.9474
7.5618
6.6901
7.2818
26
27
27
Table 65 PLL Frequency Examples
AI Rev 3.1 June 2004
67
w
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