Advanced Information
WM8753L
R53 (35h)
PLL1
Control (1)
CLKOUT1 select
0 : from MCLK pin
1 : from PLL1
5
4
3
2
1
0
5
4
3
2
1
0
CLK1SEL
CLK1DIV2
MCLK1DIV2
PLL1DIV2
PLL1RB
0
0
0
0
1
0
0
0
0
0
1
0
CLKOUT1 Divide by 2
0 : Divide by 2 disabled
1 : Divide by 2 enabled
MCLK Divide by 2
0 : Divide by 2 disabled
1 : Divide by 2 enabled
PLL1 Output Divide by 2
0 : Divide disabled
1 : Divide enabled
PLL1 reset
0 : PLL reset
1 : PLL active
PLL 1 Enable
0 : Disabled
1 : Enabled
PLL1EN
R57 (39h)
PLL2
Control (1)
CLKOUT2 select
0 : from MCLK pin
1 : from PLL2
CLK2SEL
CLK2DIV2
MCLK2DIV2
PLL2DIV2
PLL2RB
CLKOUT1 Divide by 2
0 : Divide by 2 disabled
1 : Divide by 2 enabled
MCLK Divide by 2
0 : Divide by 2 disabled
1 : Divide by 2 enabled
PLL2 Output Divide by 2
0 : Divide disabled
1 : Divide enabled
PLL2 reset
0 : PLL reset
1 : PLL active
PLL2 Enable
0 : Disabled
1 : Enabled
PLL2EN
Table 62 PLL and Clocking Control
The PLL frequency ratio R = f2/f1 (see
Figure 26 ) can be set using K and N:
N = int R
K = int (222 (R-N))
Example:
mclk=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < N < 13. There is a divide by 4 and a selectable divide by 2 after the
PLL which should be set to meet this requirement. Enabling the divide by 2 sets the required f2 = 8 x
12.288MHz = 98.304MHz.
R = 98.304 / 12 = 8.192
N = int R = 8
k = int ( 222 x (8.192 – 8)) = 805306 = C49BAh
AI Rev 3.1 June 2004
66
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
