WM8753L
Advanced Information
MASTER CLOCK AND PHASE LOCKED LOOP
The WM8753L has two on-chip phase-locked loop (PLL) circuits that can be used to:
•
Generate master clocks for the WM8753L audio functions from another external clock,
e.g. in telecoms applications.
•
Generate a clock for another part of the system from an existing audio master clock.
The user must also select the clock for the HiFi DAC, ADC and Voice DAC. The ADC and Voice DAC
are always clocked from the same clock source. The HiFi DAC may be clocked from the same or
different clock source to the ADC and Voice DAC. For HiFi Codec operation, when the ADC is
selected for high quality record, the ADC and DAC must be clocked from the same clock source. The
PLL and clock select circuit is shown below.
Figure 26 PLL and Clock Select Circuit
REGISTER
ADDRESS
R52 (34h)
Clock Control
BIT
LABEL
DEFAULT
DESCRIPTION
Control PCM clock divider
000 = divide by 1 (disable)
001 = Unused
8:6
PCMDIV[2:0]
000
010 = Divide by 3
011 = Divide by 5.5
100 = Divide by 2
101 = Divide by 4
110 = Divide by 6
111 = Divide by 8
Select internal master clock for HiFi
Codec
0: from MCLK pin
4
3
2
MCLKSEL
PCMCLKSEL
CLKEQ
0
0
1
1: from PLL1 (ensure PLL1EN=1)
Select internal master clock for
Voice Codec
0: from PCMCLK pin
1: from PLL2 (ensure PLL2EN=1)
Select clock for Voice Codec
0: PCMCLK or PLL2 clock
1: same as HiFi DAC (MCLK or
PLL1 clock)
GP1CLK1 select
0 = GP1 output
1 = CLK1 output
1
0
GP1CLK1SEL
GP2CLK2SEL
0
0
GP2/CLK2 select
0 = GP2 output
1 = CLK2 output
AI Rev 3.1 June 2004
65
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
