WM8753L
Advanced Information
GENERAL PURPOSE INPUT/OUTPUT
The WM8753L has four dual purpose input/output pins.
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•
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GP1/CLK1: General purpose output 1, or PLL1 clock output.
GP2/CLK2: General purpose output 2, or PLL2 clock output.
GPIO3: General purpose input/output 3 and control interface mode
selection input.
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GPIO4: General purpose input/output 4, or head phone detection input.
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GPIO5: General purpose input/output 5 and control interface chip/address
select input.
Pin 44 (MODE/GPIO3) is sampled on powerup to determine the control interface mode (2-wire or 3-
wire) of the WM8753L. After powerup pin 43 may be used as a GPIO, its use configurable using
GPIO3M[2:0].
Pin 45 (CSB/GPIO5) is also sampled on powerup. If 2-wire interface control mode is the value on pin
45 on powerup is used to select the 2-wire address. After powerup, if 2-wire mode is selected, pin 44
may be used as a GPIO, its use configurable using GPIO5M[1:0]. If 3-wire control interface mode is
selected pin 44 is always configured as an input and is used as the 3-wire interface latch signal.
Pin 43 (GPIO4) is a dedicated GPIO pin with TTL compatible input thresholds and CMOS output
thresholds relative to DBVDD, making it ideal for headphone detection. It also features an optional
pull-up/pull-down resistor. GPIO4M[2:0] is used to configure the GPIO4 pin.
Pins 13 and 14 (GP1/CLK1 and GP2/CLK2) are general purpose outputs and may be configured to
either output the PLL clock outputs or may be used as general purpose outputs. They are configured
using GP1M[2:0] and GP2M[2:0].
In 3-wire interface mode pin GPIO5/CSB cannot be used as a GPIO as it is used to latch the data.
Setting GPIO5M to 01, 10 or 11 will prevent the device from being written to in 3-wire mode.
GP2/CLK2 may be configured to output a clock at 256 x the ADC or Hi-Fi DAC sample rate frequency
(fs), e.g. if DAC sample rate is set to 8kHz (SR = 00110) output clock will be 256 x 8kHz =
2.048MHz.
AI Rev 3.1 June 2004
51
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
