WM8753L
Advanced Information
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRC /
VXFS
BCLK /
VXCLK
DACDAT /
ADCDAT /
VXDIN /
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
VXDOUT
MSB
LSB
MSB
LSB
Figure 17 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The
other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency
and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of
the next.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRC /
VXFS
BCLK /
VXCLK
1 BCLK
1 BCLK
DACDAT /
ADCDAT /
VXDIN /
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
VXDOUT
LSB
LSB
MSB
MSB
Figure 18 I2S Justified Audio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge
of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows
left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused
BCLK cycles between the LSB of the right channel data and the next sample.
1/fs
1 BCLK / VXCLK
LRC /
VXFS
BCLK /
VXCLK
RIGHT CHANNEL
LEFT CHANNEL
DACDAT /
ADCDAT /
VXDIN /
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
VXDOUT
MSB
LSB
Input Word Length (WL)
Figure 19 DSP Mode Audio Interface (mode A, LRP/PLRP=0)
AI Rev 3.1 June 2004
55
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
