WM8750JL
Production Data
Note: The shaded bit clock cycles are present only when 24-bit mode is selected. Please refer to the
“Bit Clock Mode” description for details.
CLOCK OUTPUT
By default ADCLRC (pin 9) is the ADC word clock input/output. Under the control of ADCLRM[1:0],
register 27(1Bh) bits [8:7] the ADCLRC pin may be configured as a clock output. If ADCLRM is 01, 10
or 11 then ADCLRC pin is always an output even in slave mode or when TRI = ‘1’, (see Table 38).
The ADC then uses the DACLRC pin as its LRCLK in both master and slave modes.
REGISTER
ADDRESS
BIT
LABEL DEFAULT
DESCRIPTION
R27(1Bh)
Additional
Control (3)
Configures ADCLRC pin
[8:7] ADCLRM
[1:0]
00
00 = ADCLRC is ADC word clock input (slave
mode) or ADCLRC output (master mode)
01 = ADCLRC pin is MCLK output
10 = ADCLRC pin is MCLK / 5.5 output
11 = ADCLRC pin is MCLK / 6 output
Table 38 ADCLRC Clock Output
CLOCKING AND SAMPLE RATES
The WM8750JL supports a wide range of master clock frequencies on the MCLK pin, and can
generate many commonly used audio sample rates directly from the master clock. The ADC and DAC
do not need to run at the same sample rate; several different combinations are possible.
There are two clocking modes:
‘Normal’ mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their multiples
(Note: fs refers to the ADC or DAC sample rate, whichever is faster)
USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in
systems with a USB interface, and eliminates the need for an external PLL to generate
another clock frequency for the audio codec.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8 (08h)
6
CLKDIV2
0
Master Clock Divide by 2
1 = MCLK is divided by 2
0 = MCLK is not divided
Sample Rate Control
Clocking Mode Select
1 = USB Mode
Clocking and
Sample Rate
Control
5:1
0
SR [4:0]
USB
00000
0
0 = ‘Normal’ Mode
Table 39 Clocking and Sample Rate Control
The clocking of the WM8750JL is controlled using the CLKDIV2, USB, and SR control bits. Setting
the CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB
mode. Each value of SR[4:0] selects one combination of MCLK division ratios and hence one
combination of sample rates (see next page). Since all sample rates are generated by dividing MCLK,
their accuracy depends on the accuracy of MCLK. If MCLK changes, the sample rates change
proportionately.
Note that some sample rates (e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their
target value by a very small amount. This is not audible, as the maximum deviation is only 0.27%
(8.0214kHz instead of 8kHz in USB mode). By comparison, a half-tone step corresponds to a 5.9%
change in pitch.
The SR[4:0] bits must be set to configure the appropriate ADC and DAC sample rates in both master
and slave mode.
Note: When the ADC is configured at a sample rate of 88.2, 88.235 or 96kHZ (SR[4:0]), the ADC right
channel data output will be delayed by one sample relative to the left channel data.
PD, April 2012, Rev 4.1
44
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
