WM8750JL
Production Data
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised in
Table 34. MS selects audio interface operation in master or slave mode. In Master mode BCLK,
ADCLRC and DACLRC are outputs. The frequency of ADCLRC and DACLRC is set by the sample
rate control bits SR[4:0] and USB. In Slave mode BCLK, ADCLRC and DACLRC are inputs.
REGISTER
ADDRESS
BIT
LABEL
BCLKINV
DEFAULT
DESCRIPTION
R7 (07h)
7
0
BCLK invert bit (for master and slave
modes)
Digital Audio
Interface
Format
0 = BCLK not inverted
1 = BCLK inverted
6
5
MS
0
0
Master / Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Left/Right channel swap
LRSWAP
1 = swap left and right DAC data in
audio interface
0 = output left and right data as normal
4
LRP
0
right, left and i2s modes – LRCLK
polarity
1 = invert LRCLK polarity
0 = normal LRCLK polarity
DSP Mode – mode A/B select
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
3:2
1:0
WL[1:0]
10
10
Audio Data Word Length
11 = 32 bits (see Note)
10 = 24 bits
01 = 20 bits
00 = 16 bits
FORMAT[1:0]
Audio Data Format Select
11 = DSP Mode
10 = I2S Format
01 = Left justified
00 = Reserved
Table 34 Audio Data Format Control
AUDIO INTERFACE OUTPUT TRISTATE
Register bit TRI, register 24(18h) bit[3] can be used to tristate the ADCDAT pin and switch ADCLRC,
DACLRC and BCLK to inputs. In Slave mode (MASTER=0) ADCLRC, DACLRC and BCLK are by
default configured as inputs and only ADCDAT will be tri-stated, (see Table 35).
REGISTER
ADDRESS
BIT
LABEL DEFAULT
TRI
DESCRIPTION
R24(18h)
Additional
Control (2)
Tristates ADCDAT and switches ADCLRC,
DACLRC and BCLK to inputs.
3
0
0 = ADCDAT is an output, ADCLRC, DACLRC
and BCLK are inputs (slave mode) or outputs
(master mode)
1 = ADCDAT is tristated, ADCLRC, DACLRC
and BCLK are inputs
Table 35 Tri-stating the Audio Interface
PD, April 2012, Rev 4.1
w
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
