Production Data
WM8750L
The output data format can be programmed by the user to accommodate stereo or monophonic
recording on both inputs. The polarity of the output signal can also be changed under software
control. The software control is shown in Table 10.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5 (05h)
ADCPOL
00 = Polarity not inverted
01 = L polarity invert
6:5
00
ADC and DAC
Control
[1:0]
10 = R polarity invert
11 = L and R polarity invert
HPOR
Store dc offset when high-pass
filter disabled
4
0
0
0
1 = store offset
0 = clear offset
ADCHPD
ADC high-pass filter enable
(Digital)
HPFLREN = 0
1 = Disable high-pass filter on left
and right channels
0 = Enable high-pass filter on left
and right channels
HPFLREN = 1
0 = High-pass enabled on left,
disabled on right
1 = High-pass enabled on right,
disabled on left
R27 (1Bh)
HPFLREN
ADC high-pass filter left or right
enable
5
0
0 = High-pass filter enable/disable
on left and right channels
controlled by ADCHPD
1 = High-pass filter enabled on left
or right channel, as selected by
ADCHPD
Table 10 ADC Signal Path Control
HPFLREN
ADCHPD
HIGH PASS MODE
High-pass filter enabled on left and right
channels
0
0
1
0
1
High-pass filter disabled on left and right
channels
0
1
1
High-pass filter enabled on left channel,
disabled on right channel
High-pass filter disabled on left channel,
enabled on right channel
Table 11 ADC High Pass Filter Enable Modes
PD, Rev 4.4, August 2012
23
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
