WM8750L
Production Data
REGISTER
ADDRESS
BIT
LABEL
ALCSEL
DEFAULT
DESCRIPTION
ALC function select
R17 (11h)
8:7
00
ALC Control 1
[1:0]
00 = ALC off (PGA gain set by register)
01 = Right channel only
(OFF)
10 = Left channel only
11 = Stereo (PGA registers unused)
Note: ensure that LINVOL and
RINVOL settings (reg. 0 and 1) are
the same before entering this mode.
MAXGAIN
[2:0]
Set Maximum Gain of PGA
111 : +30dB
6:4
3:0
111
(+30dB)
110 : +24dB
….(-6dB steps)
001 : -6dB
000 : -12dB
ALCL
[3:0]
ALC target – sets signal level at ADC
input
1011
(-12dB)
0000 = -28.5dB fs
0001 = -27.0dB fs
… (1.5dB steps)
1110 = -7.5dB fs
1111 = -6dB fs
R18 (12h)
ALCZC
ALC uses zero cross detection circuit.
7
0 (zero
cross off)
ALC Control 2
HLD
[3:0]
ALC hold time before gain is increased.
0000 = 0ms
3:0
0000
(0ms)
0001 = 2.67ms
0010 = 5.33ms
… (time doubles with every step)
1111 = 43.691s
R19 (13h)
DCY
[3:0]
ALC decay (gain ramp-up) time
0000 = 24ms
7:4
3:0
0011
ALC Control 3
(192ms)
0001 = 48ms
0010 = 96ms
… (time doubles with every step)
1010 or higher = 24.58s
ALC attack (gain ramp-down) time
0000 = 6ms
ATK
[3:0]
0010
(24ms)
0001 = 12ms
0010 = 24ms
… (time doubles with every step)
1010 or higher = 6.14s
Table 13 ALC Control
Note: For correct ALC operation in differential input mode, it is recommended that the combined
signal gain (mic boost and PGA) does not exceed 30dB when the ALC is enabled.
PD, Rev 4.4, August 2012
26
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
