Production Data
WM8580
CONTROL INTERFACE TIMING – 3-WIRE MODE
t CSS
tCSH
CSB
tSCY
t SCS
tCSS
SCLK
SDIN
LSB
t DSU
t DHO
LSB
SDO
t DL
Figure 4 SPI Compatible Control Interface Input Timing
Test Conditions
AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, TA = +25oC, fs = 48kHz, MCLK and ADCMCLK = 256fs unless
otherwise stated
PARAMETER
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
SYMBOL
tSCS
MIN
60
TYP
MAX
60/40
5
UNIT
ns
tSCY
80
ns
SCLK duty cycle
40/60
20
ns
SDIN to SCLK set-up time
SDIN hold time from SCLK rising edge
tDSU
tDHO
tDL
ns
20
ns
SDO propagation delay from SCLK rising
edge
ns
CSB pulse width high
tCSH
tCSS
tps
20
20
2
ns
ns
ns
CSB rising/falling to SCLK rising
SCLK glitch suppression
8
Table 6 3-Wire SPI Compatible Control Interface Input Timing Information
PD Rev 4.3 August 2007
15
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
