Production Data
WM8580
DIGITAL AUDIO INTERFACE – MASTER MODE
PAIFRX_BCLK/
PAIFTX_BCLK/
SAIF_BCLK
(Output)
tDL
PAIFRX_LRCLK/
PAIFTX_LRCLK/
SAIF_LRCLK
(Outputs)
tDDA
DOUT/
SAIF_DOUT
DIN1/2/3
SAIF_DIN
tDST
tDHT
Figure 2 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, PGND, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK
and ADCMCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
PAIFTX_LRCLK/
PAIFRX_LRCLK/
tDL
0
10
ns
SAIF_LRCLK propagation
delay from PAIFTX_BCLK/
PAIFRX_BCLK/
SAIF_BCLK falling edge
DOUT/SAIF_DOUT
propagation delay from
PAIFTX_BCLK/
tDDA
tDST
tDHT
0
10
ns
ns
ns
SAIF_BCLK falling edge
DIN1/2/3/SAIF_DIN setup
time to
PAIFRX_BCLK/SAIF_BCLK
rising edge
10
10
DIN1/2/3/SAIF_DIN hold
time from
PAIFRX_BCLK/SAIF_BCLK
rising edge
Table 4 Digital Audio Data Timing – Master Mode
PD Rev 4.3 August 2007
13
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
