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WM8580_07_12 参数 Datasheet PDF下载

WM8580_07_12图片预览
型号: WM8580_07_12
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道编解码器S / PDIF收发器 [Multichannel CODEC with S/PDIF Transceiver]
分类和应用: 解码器编解码器光电二极管
文件页数/大小: 97 页 / 1142 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8580  
Production Data  
TERMINOLOGY  
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output  
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).  
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.  
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB  
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).  
3. THD (dB) - THD is a ratio, of the rms values, of Distortion/Signal.  
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).  
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from  
the other. Normally measured by sending a full scale signal down one channel and measuring the other.  
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.  
MASTER CLOCK TIMING  
tMCLKL  
ADCMCLK/  
MCLK  
tMCLKH  
tMCLKY  
Figure 1 Master Clock Timing Requirements  
Test Conditions  
AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
System Clock Timing Information  
ADCMCLK and MCLK System clock  
pulse width high  
tMCLKH  
tMCLKL  
tMCLKY  
11  
11  
ns  
ns  
ns  
ADCMCLK and MCLK System clock  
pulse width low  
ADCMCLK and MCLK System clock  
cycle time  
28  
ADCMCLK and MCLK Duty cycle  
40:60  
60:40  
Table 3 Master Clock Timing Requirements  
PD Rev 4.3 August 2007  
12  
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