Production Data
WM8352
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 51 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 52 I2S Audio Interface (assuming n-bit word length)
In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A)
rising edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right
channel data immediately follows left channel data. Depending on word length, BCLK frequency and
sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the
next sample.
Figure 53 DSP/PCM Mode Audio Interface (mode A, AIF_LRCLK_INV=0)
PD, February 2011, Rev 4.4
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
