Production Data
WM8352
Table 12 shows the maximum word lengths supported for a given SYSCLK and BCLK_DIV,
assuming that one or both the ADCs and DACs are running at maximum rate.
SYSCLK
BCLK DIVIDER
BCLK_DIV
BCLK RATE (MASTER
MODE) (MHZ)
MAXIMUM WORD
LENGTH
0000 = SYSCLK / 1
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 32
1111 = SYSCLK / 32
0000 = SYSCLK / 1
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 32
1111 = SYSCLK / 32
12.288
8.192
32
32
32
32
32
20
20
16
8
6.144
4.096
3.072
2.2341818
2.048
1.536
12.288 MHz
1.117091
1.024
8
0.768
8
0.558545
0.512
N/A
N/A
N/A
N/A
N/A
32
32
32
32
32
20
20
16
8
0.384
0.384
0.384
11.2896
7.5264
5.6448
3.7632
2.8224
2.052655
1.8816
1.4112
1.026327
0.9408
0.7056
0.513164
0.4704
0.3528
0.3528
0.3528
11.2896 MHz
8
8
N/A
N/A
N/A
N/A
N/A
Table 12 BCLK Divider in Master Mode
PD, February 2011, Rev 4.4
53
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
