Production Data
WM8352
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
111 = Reserved
FLL Loop Gain
7:4
FLL_RSP_RAT
E
0000
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256
Recommended that these are not
changed from default.
2:0
FLL_RATE
[2:0]
000
Frequency of the FLL control block
000 = FVCO / 1 (Recommended value)
001 = FVCO / 2
010 = FVCO / 4
011 = FVCO / 8
100 = FVCO / 16
101 = FVCO / 32
Recommended that these are not
changed from default.
R43 (2Bh)
15:11 FLL_RATIO
[4:0]
14
CLK_VCO is divided by this integer, valid
from 1 .. 31.
FLL Control
2
(0Eh)
1 recommended for high freq reference
8 recommended for low freq reference
FLL integer multiplier N for CLK_REF
9:0
FLL_N [9:0]
FLL_K [15:0]
086h
R44 (2Ch)
15:0
C226h
FLL fractional multiplier K for CLK_REF.
This is only used if FLL_FRAC is set.
FLL Control
3
R45 (2Dh)
7
FLL_REF_FRE
Q
0
Low frequency reference locking
FLL Control
4
0 = High frequency reference locking
(recommended for reference clock >
48kHz)
1 = Lock frequency reference locking
(recommended for reference clock <=
48kHz)
5
FLL_FRAC
0
Fractional enable
0 = Integer Mode
1 = Fractional Mode
1 recommended in all cases
Select FLL input clock Source
00 = MCLK
1:0
FLL_CLK_SRC
[1:0]
00
01 = DACLRCLK
10 = ADCLRCLK
11 = CLK_32K_REF
Table 17 FLL Control Registers
PD, February 2011, Rev 4.4
57
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
