WM8352
Production Data
The field FLL_RATE controls internal functions within the FLL; it is recommended that only the
default setting be used for this parameter. FLL_RSP_RATE controls the internal loop gain and
should be set to the recommended value.
The FLL output frequency is directly determined from FLL_RATIO, FLL_OUTDIV and the real
number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the
fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the
field FLL_FRAC. It is recommended that FLL_FRAC is enabled at all times.
The FLL frequency is determined according to the following equation:
F
OUT = (FVCO / FLL_OUTDIV)
FVCO = (FREF x N.K x FLL_RATIO)
FVCO must be in the range 90-100 MHz. The value of FLL_OUTDIV should be selected as follows
according to the desired output FOUT
.
OUTPUT FREQUENCY FOUT
2.8125 MHz - 3.125 MHz
5.625 MHz - 6.25 MHz
FLL_OUTDIV
4h (divide by 32)
3h (divide by 16)
2h (divide by 8)
1h (divide by 4)
11.25 MHz - 12.5 MHz
22.5 MHz - 25 MHz
Table 16 Choice of FLL_OUTDIV
Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed
across the full range of device operating temperatures.
Once FVCO has been determined, the value of FLL_RATIO should be selected in accordance with the
recommendations in Table 17. The value of N.K can then be determined using the equation above.
FLL_REF_FREQ should be set as described in Table 17.
For best performance, FLL Fractional Mode should always be used. Therefore, if the calculations
yield an integer value of N.K, then it is recommended to adjust FLL_RATIO in order to obtain a non-
integer value of N.K.
The register fields that control the FLL are described in Table 17. Example settings for a variety of
reference frequencies and output frequencies are shown in Table 18.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R42 (2Ah)
15
FLL_ENA
0
Digital Enable for FLL
FLL Control 1
0 = disabled
1 = enabled
Note that FLL_OSC_ENA must be
enabled before enabling FLL_ENA.
14
FLL_OSC_EN
A
0
Analogue Enable for FLL
0 = FLL disabled
1 = FLL enabled
Note that FLL_OSC_ENA must be
enabled before enabling FLL_ENA.
10:8
FLL_OUTDIV
[2:0]
010
FOUT clock divider
000 = FVCO / 2
001 = FVCO / 4
010 = FVCO / 8
011 = FVCO / 16
100 = FVCO / 32
101 = Reserved
110 = Reserved
PD, February 2011, Rev 4.4
56
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
