WM8352
Production Data
12.3.3 BCLK CONTROL
In Master Mode, BCLK is derived from SYSCLK via a programmable division set by BCLK_DIV, as
described in Table 11. BCLK_DIV must be set to an appropriate value to ensure that there are
sufficient BCLK cycles to transfer the complete data words from the ADCs and to the DACs. When
the GPIO8 pin is used to provide ADCBCLK in Master mode, the clock rate on this pin is also
controlled by BCLK_DIV.
In Slave Mode, BCLK is generated externally and appears as an input to the CODEC. The host
device must provide sufficient BCLK cycles to transfer complete data words to the ADCs and DACs.
Note that, although the ADC and DAC can run at different sample rates, they share the same bit
clock BCLK in Master Mode. In the case where different ADC / DAC sample rates are used, the
BCLK frequency should be set according to the higher of the ADC / DAC bit rates. When the GPIO8
pin is used to provide ADCBCLK, and either the ADC or DAC is in Slave mode, then this restriction
does not apply.
Master/Slave operation for BCLK is controlled by the BCLK_MSTR register field.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R40 (28h)
7:4
BCLK_DIV [3:0]
0000
Sets BCLK rate for Master mode
0000 = SYSCLK
Clock Control
1
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0101 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 32
1111 = SYSCLK / 32
R115 (73h)
Audio I/F
DAC Control
14
BCLK_MSTR
0
Enables the Audio Interface BCLK
generation and enables the BCLK
pin for Master mode
0 = BCLK Slave Mode
1 = BCLK Master Mode
Table 11 BCLK Control
PD, February 2011, Rev 4.4
52
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