WM8352
Production Data
When the GPIO5 pin is configured as CODEC_OPCLK, a clock derived from SYSCLK may be output
on this pin to provide clocking for other parts of the system. The frequency of this signal is set by
OPCLK_DIV.
Alternate GPIO pins can be used to provide ADCLRCLK and ADCBCLK as described in Section 20.
An inverted L/R clock signal ADCLRCLKB can also be generated. When this feature is used, the
LRCLK and BCLK pins support the DAC only, and the alternate GPIO pins support the ADC only.
Limited capability can be provided to support mixed sample rates by this method. (The selection of
USB mode and the supported values of the various SYSCLK dividers impose restrictions on what
combinations of clocking and sample rates may be configured.)
A slow clock derived from SYSCLK may be used to provide de-bouncing of the headphone detect
function, and to set the timeout period for volume updates when zero-cross functions are used. This
clock is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE.
The overall CODEC clocking scheme is illustrated in Figure 35.
MCLK_DIV
R40[8]
1, 2
ADC
SYSCLK
MCLK
ADC_SYSCLK
fREF
fOUT
64fs
f/N
f/N
f/4
f/4
FLL
ADCLRCLK
DACLRCLK
MCLK_SEL
R40[11]
ADC_CLKDIV[2:0]
R68[2:0]
1, 1.5, 2, 3, 4, 5.5, 6
DAC
FLL_CLK_SRC
R45[1:0]
Crystal Oscillator /
GPIO 32kHz input
DAC_SYSCLK
64fs
f/N
SYSCLK
DAC_CLKDIV[2:0]
R54[2:0]
1, 1.5, 2, 3, 4, 5.5, 6
All internal clocks are derived from SYSCLK, either directly
from MCLK or via the Frequency Locked Loop (FLL). The FLL
takes MCLK, ADCLRCLK, DACLRCLK or 32kHz input as its
reference.
GP5_FN[3:0]
R141[7:4]
f/N
ADCLRCLK / CODEC_OPCLK
(GPIO5)
ADC_CLKDIV
ADC sample rate is set by ADC_CLKDIV (Master or slave
mode).
OPCLK_DIV[2:0]
R40[2:0]
1, 2, 3, 4, 5.5, 6
ADCLRCLKB
(GPIO6)
GP6_FN[3:0]
R141[11:8]
DAC_CLKDIV
DAC sample rate is set by DAC_CLKDIV (Master or slave
mode).
ADCLRC_RATE[10:0]
R70[10:0]
1 .. 2047
LRC_ADC_SEL
R41[15]
f/N
f/N
BCLKDIV
ADCLRC_ENA
R70[11]
LRCLK
(master mode output)
BCLK rate is set by BCLKDIV in Master mode.
When ADC and DAC operate at different sample rates (in
master or slave mode), BCLK rate should be high enough to
support the higher of the ADC/DAC sample rates.
DACLRC_ENA
R53[11]
BCLK
(master mode output)
f/N
BCLK_MSTR
R115[14]
ADCLRCLK, ADCBCLK
DACLRC_RATE[10:0]
R53[10:0]
1 .. 2047
These signals can be provided for the ADC via GPIO pins.
When these are used, the LRCLK and BCLK pins are used by
the DAC only.
AIF_TRI
R112[13]
BCLKDIV[3:0]
R40[7:4]
1, 1.5, 2, 3, 4, 5.5, 6, 8,
11, 12, 16, 22, 24, 32
ADCBCLK
(GPIO8)
GP8_FN[3:0]
R142[3:0]
OPCLK_DIV
GPIO Clock output frequency is set by OPCLK_DIV.
TOCLKSEL
A slow clock is used for jack detect debounce and for volume
update timeouts (when zero-crossing is enabled). The
frequency of this slow clock is set by TOCLK_RATE.
f/221
Jack detect debounce,
Volume update timeout
SLOWCLK
f/219
Other Sample Rate Controls
DEEMP configures the de-emphasis filter for the chosen
sample rate.
TOCLK_ENA
R40[15]
TOCLK_RATE
R40[14]
Figure 35 Audio CODEC Clocking
PD, February 2011, Rev 4.4
48
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
