Production Data
WM8352
The applicable register bits are defined in Table 135.
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R12 (0Ch)
Power
Mgmt (5)
11
RTC_TICK_ENA
1
Enable RTC counting (instruction only)
0 = disabled
1 = enabled
Protected by security key.
R218 (DAh)
RTC Tick
Control
15
14
RTC_TICKSTS
RTC_TRIM [9:0]
0
Status of tick request. This bit can be
used to ensure the RTC is using the value
of RTC_TICK_ENA.
0 = disabled
1 = enabled
Protected by security key.
9:0
00_0000_ RTC frequency trim. Used to adjust the
0000
count value of the Tick Gen block to
compensate for crystal inaccuracies.
RTC frequency trim is a 10bit fixed point
<4,6> 2's complement number. MSB
Scaling = -8Hz. The register indicates the
error (in Hz) with respect to the ideal
32768Hz) of the input crystal frequency.
e.g.:
Actual crystal freq: 32769.00Hz:
Required trim 0xb0001_000000
(+1.000000)
Actual crystal freq: 32767.00Hz:
Required trim 0xb1111_000000 (-
1.000000)
Actual crystal freq: 32775.58Hz:
Required trim 0xb0111_100101
(+7.578125)
Actual crystal freq: 32763.78Hz:
Required trim 0xb1011_110010 (-
4.218750)
Protected by security key.
Note: RTC_TICK_ENA can be accessed through R12 or through R218. Reading from or writing to
either register location has the same effect.
Table 135 Controlling the RTC Frequency Trim
PD, February 2011, Rev 4.4
193
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
