WM8200
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DEVICE DESCRIPTION
INTRODUCTION
The WM8200 is a high speed analogue to digital converter (ADC) with on-chip analogue pre-
processing and reference generation, deisgned for applications such as composite video digitisation
digital copiers and high speed data acquisition. The integrated clamp and the coarse offset function
mean the device is ideally suited to CCD/CMOS input systems such as colour scanners, digital
copiers and digital cameras. A wide input voltage range between REFB and REFT allows the
WM8200 to be used in both imaging and communications systems.The chip architecture consists of:
•
High bandwidth sample and hold input, which can operate in differential or single-
ended mode
•
•
Programmable gain amplifier (PGA)
Voltage clamp for DC restoration that can take its reference from an on-chip 10-bit
DAC or an external source
•
•
•
Coarse offset function to allow clamping with single ended CCD style inputs
10-bit, 40MSPS pipeline analogue-to-digital converter (ADC) core
On-chip reference generator and reference buffer (external references can also be
used for applications where common or high precision references are required)
•
10-bit parallel output for ADC conversion. ADC data can be output in unsigned binary
or two’s complement format. An out-of-range output pin indicates when the input signal
is outside the converter’s range
•
Serial control interface to configure the operation of the device.
ANALOGUE SIGNAL PATH
The WM8200 analogue signal path consists of a DC clamp with a 10-bit clamp level DAC (discussed
under ‘DC Clamp’, below), a high-bandwidth sample and hold unit followed by a programmable gain
amplifier (PGA) and a fast 10-bit pipelined analogue to digital converter (ADC core).
REFT
VP+
VP-
VQ+
VQ-
AINP
AINN
X
SAMPLE
AND
HOLD
ADC
CORE
PGA
X-1
REFB
Figure 2 Analogue Input Signal Flow
Figure 2 shows the signal flow through the sample and hold unit and the PGA to the ADC core,
where the process of analogue to digital conversion is performed against the ADC reference
voltages, REFT and REFB (their generation from internal or external reference sources is described
later).
SAMPLE AND HOLD
The differential analogue input signals can be connected directly to the AINN and AINP pins, either
DC coupled, AC coupled, or AC coupled with DC restoration using the WM8200 clamp circuit.
The differential sample and hold processes VINP and VINN with respect to the voltages applied to the
REFT and REFB pins, and produces a differential output VP = VP+ - VP- given by:
VP = AINP − AINN
For single-ended input signals, the signal can be DC or AC coupled to either AINN or AINNP, and a
suitable reference voltage must be applied to the other pin. Note of the input signal is applied to
AINN this will result in it being inverted during sampling.
PP Rev 1.22 March 2002
7
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
