WM8200
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Test Conditions:
AVDD = DVDD = 3.0V, fCLK = 40MHz, 50% duty cycle, MODE = AVDD, VREF=1.0V (REFT = 2.0V, REFB = 1.0V),
PGA gain = 1.0, TA = TMIN to TMAX, unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supplies
MODE = AGND
MODE = AVDD
CL = 10pF
28.5
31
5
mA
mA
mA
Analogue supply current
IAVDD
Digital supply current
IDVDD
Standby power consumption
(digital and analogue combined)
I
VDD(STBY)
75
uW
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
(Note 1)
(Note 1)
0.2 x VDD
0.4
V
V
V
V
Input HIGH level
0.8 x VDD
VDD – 0.4
Output LOW
VOL
VOH
IOL = -50µA
IOH = 50µA
Output HIGH
Notes
1. Digital input and output levels refer to the supply used for the input/output buffer on the relevant pin. CLK and MODE
refer to the AVDD supply, all other digital input/output refers to the DVDD supply.
CONTROL INTERFACE TIMING
tCSL
tCSH
CSB
tSCY
tCSS
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
Figure 1: Control Interface Timing
Test Conditions
AVDD = DVDD = 3.0V, AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise stated
PARAMETER SYMBOL TEST CONDITIONS MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising
edge
tSCS
60
ns
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
80
30
30
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
CSB pulse width high
CSB rising to SCLK rising
Table 1 Control Interface Timing Information
PP Rev 1.22 March 2002
6
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
