WM8200
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CONTROL INTERFACE
The internal control registers are programmable via the 3-wire serial interface. SDIN is used for the
program data, SCLK is used to clock in the data and CSB is used to latch in the program data. The
3-wire interface protocol is shown in Figure 6.
CSB
SCLK
SDIN
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ADDRESS
DATA
Figure 6: 3-Wire Serial Interface
1. A[3:0] are Control Address Bits
2. D[7:0] are Control Data Bits
3. CSB is edge sensitive – the data is latched on the rising edge of CSB.
REGISTER MAP
Table 3 shows the location of each control bit used to determine the operation of the WM8200. The
procedure for programming the register map is described in the CONTROL INTERFACE section.
ADDR
NAME
DEFAULT
(HEX)
BIT
B7
B6
B5
B4
B3
B2
B1
B0
0000 Clamp Reg 1
00
00
01
DAC[7]
DAC[6]
DAC[5]
DAC[4]
0
DAC[3] DAC[2]
DAC[1]
DAC[9]
PGA[1]
CLDIS
DAC[0]
DAC[8]
PGA[0]
PD
0001
0010
0
0
0
0
PGASENSE
0
Clamp Reg 2
PGA Control
Control
0
0
0
0
0
0
PGAOFF
CLPSEL
PGA[2]
TWOSC
0011
00
OEB
0100 -
1111
Reserved
00
Reserved, do not write to these register locations
Table 3: Register Map
PP Rev 1.22 March 2002
11
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
