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W9412G6JH-5 参数 Datasheet PDF下载

W9412G6JH-5图片预览
型号: W9412G6JH-5
PDF下载: 下载PDF文件 查看货源
内容描述: 双倍数据速率的架构;每个时钟周期2的数据传输 [Double Data Rate architecture; two data transfers per clock cycle]
分类和应用: 存储内存集成电路光电二极管动态存储器双倍数据速率数据传输时钟
文件页数/大小: 53 页 / 1006 K
品牌: WINBOND [ WINBOND ]
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W9412G6JH  
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and  
voltage, over the entire temperature and voltage range. For a given output, it represents the  
maximum difference between pullup and pulldown drivers due to process variation.  
f. Verified under typical conditions for qualification purposes.  
g. TSOP II package devices only.  
h. Only intended for operation up to 266 Mbps per pin.  
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below  
0.5 V/nS as shown in Table 2. The Input slew rate is based on the lesser of the slew rates  
determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.  
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew  
rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise,  
fall rate and DC-DC delta rise, fall rate. Input slew rate is based on the lesser of the slew rates  
determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.  
The delta rise/fall rate is calculated as:  
{1/(Slew Rate1)}-{1/(slew Rate2)}  
For example: If Slew Rate 1 is 0.5 V/nS and Slew Rate 2 is 0.4 V/nS, then the delta rise, fall rate is  
-0.5 nS/V. Using the table given, this would result in the need for an increase in tDS and tDH of 100  
pS.  
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/nS. The  
I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate. The input  
slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC)  
to VIL(DC), and similarly for rising transitions.  
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve  
setup and hold times. Signal transitions through the DC region must be monotonic.  
Publication Release Date: Nov. 29, 2011  
- 34 -  
Revision A03  
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