Preliminary W91030B
tRF
tRR
VHM
VCT
VLM
FDRN
tRL
VHM = 0.7 VDD , VCT = 0.5 V
= 0.3 VDD
, V
LM
DD
Figure 8-5. FDRN Output Timing
1st byte data
2nd byte data
stop
stop
start
start
0
start
Tip/Ring
1*
1
b0 b1 b2 b3 b4 b5 b6 b7 1*
1
0
b0 b1 b2 b3 b4 b5 b6 b7
1
0
b0
tIDD
1st byte data
2nd byte data
stop
stop
start
start
start
DATA
DCLK
b0 b1 b2 b3 b4 b5 b6 b7
1/fDCLK0
b0 b1 b2 b3 b4 b5 b6 b7
tCRD
tRL
FDRN
* Mark bit or redundant stop bit(s), will be omitted.
Figure 8-6. Serial Data Interface Timing of FSK Demodulation in Mode 0
VHM
VLM
DCLK
tR1
V
= 0.3 VDD
HM = 0.7 VDD , V
LM
Figure 8-7. DCLK Mode 1 Input Timing
Publication Release Date: March 2000
Revision A1
- 19 -
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