W90N745CD/W90N745CDG
Control Register (CAHCON)
Cache controller supports one Control register used to control the following operations.
y
y
y
y
Flush I-Cache and D-Cache
Load and lock I-Cache and D-Cache
Unlock I-Cache and D-Cache
Drain write buffer
These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command
set bit will be cleared to “0” automatically.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
CAHCON
R/W Cache control register
0xFFF0_2004
0x0000_0000
31
23
15
30
22
14
29
21
13
28
27
19
11
3
26
18
10
25
17
9
24
16
8
RESERVED
20
RESERVED
12
RESERVED
4
7
6
5
2
1
0
DRWB
ULKS
ULKA
LDLK
FLHS
FLHA
DCAH
ICAH
BITS
DESCRIPTION
[31:8]
RESERVED
DRWB
-
Drain write buffer
[7]
Forces write buffer data to be written to main memory.
Unlock I-Cache/D-Cache single line
[6]
ULKS
ULKA
Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in
CAHADR register must be specified.
Unlock I-Cache/D-Cache entirely
[5]
[4]
Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared
to 0.
Load and Lock I-Cache/D-Cache
Loads the instruction or data from external memory and locks into
cache. Both WAY and ADDR bits in CAHADR register must be
specified.
LDLK
- 86 -
WINBOND [ WINBOND ]
