W90N745CD/W90N745CDG
Cache Test Register 0 (CTEST0)
Cache test control register that configures the cache and tag ram testing enable or disable. In addition,
this register controls the built-in-self-test (BIST) function of SRAM.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
CTEST0
R/W Cache test register 0
0x0000_0000
0xFFF6_0000
31
23
30
22
14
29
21
13
28
27
19
11
26
18
10
25
17
9
24
16
8
RESERVED
20
RESERVED
12
15
BISTEN
7
RESERVED
5
BST_GP3 BST_GP2 BST_GP1 BST_GP0
6
4
3
2
1
0
RESERVED
CATEST
BITS
DESCRIPTION
[31:16]
RESERVED
BISTEN
-
BIST mode enable
[15]
[14:12]
[11]
When set to “1”, BIST mode will be enabled, the selected memory
groups begins to be tested by BIST.
RESERVED
BIST_GP3
-
Memory group 3 is selected to test by BIST
When set to “1”, memory group 3, including data cache tag ram
way 0 and way 1, are selected to be tested by BIST.
Memory group 2 is selected to test by BIST
[10]
[9]
BIST_GP2
BIST_GP1
When set to “1”, memory group 2, including program cache tag
ram way 0 and way 1, are selected to be tested by BIST.
Memory group 1 is selected to test by BIST
When set to “1”, memory group 1, including data cache ram way 0
and way 1, are selected to be tested by BIST.
Memory group 0 is selected to test by BIST
[8]
BIST_GP0
When set to “1”, memory group 0, including program cache ram
way 0 and way 1, are selected to be tested by BIST.
[7:0]
RESERVED
-
** Note: The 4 memory groups can be selected and tested simultaneously by BIST.
Publication Release Date: September 22, 2006
Revision A2
- 89 -
WINBOND [ WINBOND ]
