W90N745CD/W90N745CDG
Cache Test Register 1 (CTEST1)
Cache Test Register that will be read back to provide the status of cache RAM BIST. Whether the BIST
is finish and all of bank of SRAM are tested successfully will be presented in this register.
REGISTER
ADDRESS
R/W
DESCRIPTION
Cache test register 1
RESET VALUE
CTEST1
R
0xFFF6_0004
0x0000_0000
31
FINISH
23
30
22
14
6
29
21
13
5
28
27
RESERVED
19
26
18
10
25
17
9
24
16
8
20
RESERVED
15
12
11
3
RESERVED
4
7
2
1
0
BFAIL7
BFAIL6
BFAIL5
BFAIL4
BFAIL3
BFAIL2
BFAIL1
BFAIL0
BITS
DESCRIPTION
BIST completed
This bit is “0” initially. When BIST mode enabled, this bit will be “1”
after BIST test completed. The values of BFAIL0-7 are valid only
after FINISH = 1.
[31]
FINISH
[30:8]
[7]
RESERVED
BFAIL7
-
BIST test fail for data cache tag ram way 1
If this bit equals to “1”, it indicates the data cache tag ram for way
1 is tested fail by BIST. “0” means the test is passed.
BIST test fail for data cache tag ram way 0
[6]
[5]
[4]
[3]
BFAIL6
BFAIL5
BFAIL4
BFAIL3
If this bit equals to “1”, it indicates the data cache tag ram for way
0 is tested fail by BIST. “0” means the test is passed.
BIST test fail for instruction cache tag ram way 1
If this bit equals to “1”, it indicates the instruction cache tag ram for
way 1 is tested fail by BIST. “0” means the test is passed.
BIST test fail for instruction cache tag ram way 0
If this bit equals to “1”, it indicates the instruction cache tag ram for
way 0 is tested fail by BIST. “0” means the test is passed.
BIST test fail for data cache ram way 1
If this bit equals to “1”, it indicates the data cache ram for way 1 is
tested fail by BIST. “0” means the test is passed.
- 90 -
WINBOND [ WINBOND ]
