W90N745CD/W90N745CDG
Timing Control Registers （SDTIME0/1）
W90N745 offers the flexible timing control registers to control the generation and processing of the
control signals and can achieve you use different speed of SDRAM
REGISTER
SDTIME0
SDTIME1
ADDRESS
R/W
DESCRIPTION
RESET VALUE
0x0000_0000
0x0000_0000
0xFFF0_1010
R/W SDRAM bank 0 timing control register
R/W SDRAM bank 1 timing control register
0xFFF0_1014
31
23
15
7
30
22
14
29
21
13
28
27
19
26
18
10
2
25
17
9
24
16
8
RESERVED
20
12
RESERVED
11
3
RESERVED
5
tRCD
1
6
4
0
tRDL
tRP
tRAS
BITS
DESCRIPTION
[31:11]
RESERVED
-
SDRAM bank 0/1, /RAS to /CAS delay
tRCD [10:8]
MCLK
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
[10:8]
tRCD
SDRAM bank 0/1, Last data in to pre-charge command
tRDL [7:6]
MCLK
0
0
1
0
1
1
2
3
4
[7:6]
tRDL
0
1
1
Publication Release Date: September 22, 2006
Revision A2
- 69 -
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