W90N745CD/W90N745CDG
Configuration Registers（SDCONF0/1）
The configuration registers enable software to set a number of operating parameters for the SDRAM
controller. There are two configuration registers SDCONF0、SDCONF1 for SDRAM bank 0、bank 1
respectively. Each bank can have a different configuration.
REGISTER
SDCONF0
SDCONF1
ADDRESS
0xFFF0_1008
0xFFF0_100C
R/W
DESCRIPTION
RESET VALUE
0x0000_0800
0x0000_0800
R/W SDRAM bank 0 configuration register
R/W SDRAM bank 1 configuration register
31
23
15
30
22
29
21
28
BASADDR
27
19
11
3
26
18
10
2
25
17
24
16
20
12
4
BASADDR
13
RESERVED
14
9
RESERVED
1
8
0
MRSET RESERVED AUTOPR
LATENCY
COLUMN
7
6
5
COMPBK
DBWD
SIZE
BITS
DESCRIPTION
Base address pointer of SDRAM bank 0/1
The start address is calculated as SDRAM bank 0/1 base pointer
<< 18. The SDRAM base address pointer together with the “SIZE”
bits constitutes the whole address range of each SDRAM bank.
[31:19]
BASADDR
[18:16]
[15]
RESERVED
MRSET
-
SDRAM Mode register set command for SDRAM bank 0/1
This bit set will issue a mode register set command to SDRAM.
-
[14]
RESERVED
Auto pre-charge mode of SDRAM for SDRAM bank 0/1
Enable the auto pre-charge function of external SDRAM bank 0/1
0 = Auto pre-charge
[13]
AUTOPR
1 = No auto pre-charge
The CAS Latency of SDRAM bank 0/1
Defines the CAS latency of external SDRAM bank 0/1
LATENCY [12:11]
MCLK
[12:11]
LATENCY
0
0
1
1
0
1
0
1
1
2
3
REVERSED
Publication Release Date: September 22, 2006
Revision A2
- 67 -
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