W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
Address bus alignment for external I/O bank 0~3
When ADRS is set, external address (A20~A0) bus is alignment to byte
address format, that is, A0 is internal AHB address bus HADDR[0] and A1 is
AHB bus HADDR[1] and so forth. And it ignores DBWD [1:0] setting.
[15]
ADRS
Access cycles of external I/O bank 0~3
This parameter means nWE, nWBE and nOE active time clock. Detail timing
diagram please refer to Figure 6.3.6 and 6.3.7
tACC[14:11]
MCLK
tACC[14:11]
MCLK
9
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reversed
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
11
[14:11]
tACC
13
15
17
19
21
23
Chip selection hold time of external I/O bank 0~3
This parameters control nWBE and nOE hold time. Detail timing diagram
please refer to Figure 6.3.6 and 6.3.7
tCOH [10:8]
MCLK
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
[10:8]
tCOH
Publication Release Date: September 22, 2006
Revision A2
- 73 -
WINBOND [ WINBOND ]
