W90N745CD/W90N745CDG
EBI Control Register (EBICON)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
EBICON
R/W EBI control register
0xFFF0_1000
0x0001_0000
31
23
15
7
30
29
28
20
12
4
27
EXBE3
19
26
EXBE2
18
25
EXBE1
17
24
EXBE0
16
RESERVED
21
22
14
6
RESERVED
13
REFEN
10
REFMOD
9
CLKEN
8
11
REFRAT
5
3
2
1
0
REFRAT
WAITVT
LITTLE
BITS
DESCRIPTION
[31:27]
RESERVED
EXBE3
External IO bank 3 byte enable
This function is used for some devices that with high and low bytes
enable signals to control which byte will be write or mask data output
when read. For this kind device, software can set this bit HIGH to
implement this function. Detail pin interconnection is showed as Figure
6.3.8.
[27]
1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write
strobe signal to SRAM.
0 = nWBE[1:0] pin is byte write strobe signal.
External IO bank 2 byte enable
The bit function description is the same as EXBE3 above.
[26]
[25]
EXBE2
EXBE1
1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write
strobe signal to SRAM.
0 = nWBE[1:0] pin is byte write strobe signal.
External IO bank 1 byte enable
The bit function description is the same as EXBE3 above.
1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write
strobe signal to SRAM
0 = nWBE[1:0] pin is byte write strobe signal
Publication Release Date: September 22, 2006
- 61 -
Revision A2
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