W90N745CD/W90N745CDG
6.3.2.1. SDRAM Components Supported
Table 6.3.1 SDRAM supported by W90N745
TYPE BANKS ROW ADDRESSING
RA0~RA10
SIZE
COLUMN ADDRESSING
CA0~CA8
2Mx8
1Mx16
8Mx8
2
16M bits
2
4
4
4
4
4
4
RA0~RA10
RA0~RA11
RA0~RA11
RA0~RA11
RA0~RA11
RA0~RA12
RA0~RA12
CA0~CA7
CA0~CA8
64M bits
128M bits
256M bits
4Mx16
16Mx8
8Mx16
32Mx8
16Mx16
CA0~CA7
CA0~CA9
CA0~CA8
CA0~CA9
CA0~CA8
AHB Bus Address Mapping to SDRAM Bus
Note: * indicates the signal is not used; ** indicates the signal is fixed at logic 0 and is not used;
The HADDR prefixes have been omitted on the following tables.
A14 ~ A0 are the Address pins of the W90N745 EBI interface;
A14 and A13 are the Bank Select Signals of SDRAM.
Publication Release Date: September 22, 2006
- 57 -
Revision A2
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