W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
External IO bank 0 byte enable
This bit function description is the same as EXBE3 above.
[24]
EXBE0
1 = nWBE[1:0] pin is byte enable signals, nWE will be used as write
strobe signal to SRAM
0 = nWBE[1:0] pin is byte write strobe signal
[23:19]
[18]
RESERVED
REFEN
-
Enable SDRAM refresh cycle for SDRAM bank0 & bank1
This bit set will start the auto-refresh cycle to SDRAM. The refresh rate is
according to REFRAT bits.
1 = enable refresh function
0 = disable refresh function
Refresh mode of SDRAM for SDRAM bank
Defines the refresh mode type of external SDRAM bank
Software can write this bit “1” to force SDRAM enter self-refresh mode.
0 = Auto refresh mode
[17]
REFMOD
1 = Self refresh mode
NOTE: If any read/write to SDRAM occurs then this bit will be cleared to
“0” by hardware automatically and SDRAM will enters auto-refresh
mode.
Clock enable for SDRAM
Enables the SDRAM clock enable (CKE) control signal
0 = Disable (power down mode)
1 = Enable （Default）
[16]
CLKEN
Refresh count value for SDRAM
The SDRAM Controller automatically provides an auto refresh cycle for
every refresh period programmed into the REFRAT bits when the
REFEN bit of each bank is set
[15:3]
REFRAT
value
The refresh period is calculated as period =
fMCLK
- 62 -
WINBOND [ WINBOND ]
