W90N745CD/W90N745CDG
I²S Clock Control Register (I²SCKCON)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
I²SCKCON
I²S PLL clock Control Register
0xFFF0_0014
R/W
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
26
18
10
2
25
17
9
24
16
8
RESERVED
19
RESERVED
11
RESERVED
I²SPLLEN
4
3
1
0
PRESCALE
BITS
DESCRIPTION
[31:9]
RESERVED
I²SPLLEN
-
I²S PLL clock source enable
Set this bit will enable PLL1 clock output to audio I²S clock input.
1 = Enable PLL1 clock source for audio I²S
[8]
0 = Disable PLL1 clock source for audio I²S
The PLL1 is used by I²S, if in use, software can using this
prescaler to generate an appropriate clock nearly 12.288M or
16.934M. The clock is generated as below, and if PRESCALE =0,
the PLL_AUDIO is the same frequency as FOUT “PLL_AUDIO =
PLL_FOUT/(PRESCALE +1)”
[7:0]
PRESCALE
Publication Release Date: September 22, 2006
- 51 -
Revision A2
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