W90N745CD/W90N745CDG
EXTAL
FIN
Input Divider
(NR)
PLL1
INDV1[4:0]
FBDV1[8:0]
Output
Divider
(NO)
Charge
Pump
480MHz
FOUT
to Audio Controller
PFD
VCO
Feedback
Divider
(NF)
OTDV1[1:0]
Figure 6.2.11 Audio PLL block diagram
The formula of output clock of PLL is:
NF
1
FOUT = FIN ∗
∗
NR NO
FOUT:Output clock of Output Divider
FIN:External clock into the Input Divider
NR:Input divider value (NR = INDV1 + 2)
NF:Feedback divider value (NF = FBDV1 + 2)
NO:Output divider value (NO = OTDV1)
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