W90N745CD/W90N745CDG
Power Management Control Register (PMCON)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
PMCON
Power Management Control Register
0xFFF0_0028
R/W
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
27
26
18
10
25
17
9
24
16
8
RESERVED
20
19
RESERVED
12
11
RESERVED
3
4
2
1
0
RESERVED
MIDLE
PD
IDLE
BITS
DESCRIPTION
[31:3]
RESERVED
MIDLE
Memory controller IDLE enable
Setting both MIDLE and IDLE bits HIGH will let memory controller
enter IDLE mode, the clock source of memory controller will be halted
while ARM CORE enter IDLE mode.
[2]
1=memory controller will be forced into IDLE mode, (clock of memory
controller will be halted), when IDLE bit is set.
0 = memory controller still active when IDLE bit is set.
NOTE: Software must let SDRAM enter self-refresh mode before
enable this function because SDRAM MCLK will be stopped.
Power down enable
Setting this bit HIGH will let W90N745 enter power saving mode. The
clock source 15M crystal oscillator and PLLs are stopped to generate
clock. User can use nIRQ[3:0], keypad and external RESET to wakeup
W90N745.
[1]
[0]
PD
1 = Enable power down
0 = Disable
IDLE mode enable
Setting this bit HIGH will let ARM Core enter power saving mode. The
peripherals can still keep working if the clock enable bit in CLKSEL is
set. Any nIRQ or nFIQ to ARM Core will let ARM CORE to exit IDLE
state.
IDLE
1 = IDLE mode
0 = Disable
- 54 -
WINBOND [ WINBOND ]
