W90N745CD/W90N745CDG
MII Management Control and Address Register (MIIDA)
The EMC provides MII management function to access the control and status registers of the external
PHY. The MIIDA register is used to keep the MII management command information, like the register
address, external PHY address, MDC clocking rate, read/write etc.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
MII Management Control and Address
Register
MIIDA
0xFFF0_3098
R/W
0x0090_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
Reserved
19
26
25
17
24
16
22
MDCCR
14
18
MDCON
PreSP
10
BUSY
9
Write
8
11
3
Reserved
6
PHYAD
2
1
0
Reserved
PHYRAD
BITS
DESCRIPTIONS
[31:24]
Reserved
MDCCR
-
The MDC Clock Rating controls the MDC clock rating for MII
Management I/F.
Depend on the IEEE Std. 802.3 clause 22.2.2.11, the minimum
period for MDC shall be 400ns. In other words, the maximum
frequency for MDC is 2.5MHz. The MDC is divided from the AHB bus
clock, the HCLK. Consequently, for different HCLKs the different
ratios are required to generate appropriate MDC clock.
[23:20]
The following table shows relationship between HCLK and MDC
clock in different MDCCR configurations. The THCLK indicates the
period of HCLK.
The MDC Clock ON Always controls the MDC clock generation. If the
MDCON is set to high, the MDC clock actives always. Otherwise, the
MDC will only active while S/W issues a MII management command.
[19]
MDC
1’b0: The MDC clock will only active while S/W issues a MII
management command.
1’b1: The MDC clock actives always.
- 122 -
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